Field of the Invention
The embodiments of the invention relate to a built-in gate driver and, more particularly, to a built-in gate driver capable of improving output characteristics of the gate driver by reducing load of clock lines and a display device using the same.
Discussion of the Related Art
Flat panel display devices include Liquid Crystal Displays (LCDs) using liquid crystal, Organic Light Emitting Diode (OLED) displays using OLEDs, and Electrophoretic Displays (EPDs) using electrophoretic particles. In more detail, a flat panel display device includes a display panel for displaying an image through a pixel array in which each pixel is independently driven by a Thin Film Transistor (TFT), a panel driver for driving the display panel, and a timing controller for controlling the panel driver. The panel driver includes a gate driver for driving gate lines of the display panel and a data driver for driving data lines of the display panel. Recently, the gate driver has mainly used a Gate-In-Panel (GIP) type which is formed together with a TFT array of a pixel array and is built in the display panel.
FIG. 1 is a diagram schematically illustrating a configuration of a related art built-in gate driver. Referring to FIG. 1, the built-in gate driver includes a shift register located in a non-display region of a display panel. The shift register includes stages ST1 to STn dependently connected to each other to individually drive gate lines G1 to Gn of the display panel and each stage includes a plurality of TFTs. The shift register also includes clock lines CLs for supplying clocks and power lines PLs for supplying power voltages. As shown, clock lines CLs and the power lines PLs are arranged in parallel at the outer side of the shift register in the proximity of the stages ST1 to STn.
However, the stages ST1 to STn have a problem with an increase in output delay in the direction of the bottom from the top thereof. The output delay of each stage is affected by a clock delay generated while a clock reaches an output TFT of a corresponding stage and the clock delay is affected by resistance and parasitic capacitance of a clock line.
In particular, the parasitic capacitance of a clock line includes parasitic capacitance of an output TFT connected to the clock line and an overlap capacitance caused by overlap between the clock line or another clock line and a power line. Generally, a polycrystalline silicon TFT or an oxide TFT using a coplanar structure has a relatively small parasitic capacitance of an output TFT, because the source and drain electrodes do not overlap the gate electrode. Therefore, the overlap capacitance caused by the overlap between the clock line and other lines has a relatively great effect on the clock delay.